1. Field of the Invention
The invention relates generally to the field of logic circuit testing, and more specifically to providing an indication of the propagation delay of logic under test.
2. Background Art
Given the increasing complexity and density of current integrated circuit logic chips, the need to test the operation of the logic in a reliable and efficient manner has become more acute. One such test methodology is the so-called "level-sensitive scan design," or LSSD, test. Briefly, in LSSD testing, a chain of shift register latches (SRLs) are coupled to the inputs and outputs of the internal logic under test. Test data is scanned serially into one chain (the input chain) of shift register latches. When the input shift register is full, the data propagates through the logic under test (LUT), and is written into a second chain (the output chain) of SRLs. The acquired data is then scanned serially out and compared to the expected data. The LSSD test indicates that the logic is not functioning properly when the acquired data does not match the expected data. This general type of functionality test is referred to as "stuck fault" testing, because it determines the existence of permanent (or "stuck") errors in the logic under test.
However, in addition to confirming the functionality of the logic under test, it is also desirable to check the propagation delay through the logic. That is, even if the stuck fault test confirms that the logic achieves the desired function, the circuit will not meet its performance specifications if it cannot produce the logic signals within the allocated time. Tests that determine propagation delays and detect propagation delay failures are referred to as "performance" or transition fault tests.
There are several references that disclose logic test methodologies that provide both stuck fault and performance testing. In such systems, a critical path is defined in the logic. The test signals must propagate through this critical path within a set amount of time. Thus, stuck fault test results are provided by comparing the expected with the acquired data as described above; performance test results are provided in that if the signals do not propagate through the critical path in time, they will not be received, indicating a performance fault. See an article by komonytsky entitled, "Synthesis of Techniques Creates Complete System Self-Test", Electronics, Mar. 10, 1983, pp. 110-115; see also U.S. patent application Ser. No. 062,310 entitled, "Improved Delay Testing for High Speed Logic", filed Jun. 15, 1987 by Beh et al and assigned to the assignee of the present invention.
However, these techniques are impossible to implement on testers without multiple timing sets. These difficulties will be discussed below with reference to FIGS. 1 and 2, which show a conceptualized LSSD block diagram and cycle timing, respectively, for a conventional stuck fault test carried out using a test system capable of performing LSSD stuck fault tests.
As shown in FIG. 1, an SRL chain 10 is made up of two pairs 12, 14 of SRL master and slave latches L1, L2. The L1 latch of the first SRL pair l2 receives as logic inputs a first clock signal A/C, a second control signal SG (or "scan gate"); a third data signal SI0 (or "scan-in"), and a fourth data signal DI0. The L2 latch of the first SRL 12 receives as logic inputs the L1 output (not shown) and a clock signal B. The output of the first L2 latch is the SI1 data input of the L1 latch of the second SRL pair 14. Note also that the data signal DI1 is different from the data signal DI0. The remaining elements of the second SRL pair 14 are the same as those of the first SRL pair described above. In the output SRL chain 20, notice that DI0 and DI1 inputs to the L1 latches are taken from the outputs of the logic under test (box labeled "Combinational Logic (LUT)"). The remaining elements of the output SRLs receive the same inputs and provide substantially the same functions as the input SRL described above.
In operation, when the SG signal selects scan (or serial) mode, the data at the scan input SI0 or SI1 will be acquired by the L1 latch when the A/C clock pulses (by "pulse" we mean rises or falls, whichever makes the clock active. In the waveform diagram of FIG. 2, the A/C clock "pulses" when it rises). When the SG signal selects parallel mode, the data at the data input DI0 or DI1 will be acquired by the L1 latch when the A/C clock pulses. Thus, the state of the SG clock determines from which input data will be acquired by the L1 latches.
In the L2 latch, data is acquired from the L1 by pulsing the B clock. Data is generally available to the LUT directly from the L2 slave latch. Note that the output of the L2 latch is also fed, as the SI1 input, to the second L1 in each SRL chain. Thus, when SG is in serial mode and the A/C clock pulses, the L1 latches acquire the data provided by the immediately preceeding L2 latch. When SG is in parallel mode and the A/C clock pulses, the output of the previous L2 is ignored and the L1's acquire data provided at the DI0, DI1 inputs.
The conventional operation of the input and output SRL chains will now be explained in more detail with reference to the waveform diagrams of FIG. 2. The cycles C1-C8 are machine (or timing) cycles of the tester that produces the test signals. Each machine cycle introduced a new test vector or test pattern to the device under test. Such a machine cycle is usually very long in relation to the inherent speed of the device. A tester machine cycle may be more than 50.times. the length of delay through the device under test. During the first few machines cycles (C1, C2) the SG signal indicates that the SRLs are in serial mode. During these cycles, test data is provided one bit at a time at the SI0 input to the L1 latch of SRL pair 12. In cycle C1, a first test bit is latched by the first SRL pair 12 (i.e., the A/C clock pulses to cause the L1 to latch the test bit, and then the B clock pulses to cause the L2 to latch the test bit). In cycle C2, the first test bit (available at the SI1 input from the L2 latch of SRL pair 12) is latched by the second SRL pair 14, and a second test bit is latched by the first SRL pair 12. Thus, by the end of cycle C2, the first test bit is provided at the L2 output of the second SRL pair 14 and the second test bit is provided at the L2 output of the first SRL pair 12.
In this particular example, by the end of cycle C2 the serial scan of test data is complete. In practice, there would be many more pairs of L1-L2 latches in the input SRL than the two SRL pairs shown in FIG. 1; however, it is to be understood that the present operational description applies equally well to such implementations wherein the two L1-L2 pairs shown in FIG. 1 constitute the last two SRL pairs of the input SRL chain. Similarly, in practice, there may be several such chains of L1, L2 latch pairs which feed data to the logic of the device under test. All such L1 and L2 would be controlled simultaneously in the same manner as described herein.
In cycle C3, the SG clock changes to switch from serial mode to parallel mode. Note that no other clock signals change state during this cycle, in order to ensure that the SG clock has fully propagated before proceeding.
In cycle C4, when the A/C clock pulses data presented at the DI0, DI1 inputs of the SRLs is acquired by the L1s. In the output SRL chain 20, the logic data (or data bits) from the LUT are available at the inputs DI0 and DI1 of the third and fourth SRL pairs 22, 24 respectively. Since SG is in parallel mode, whatever data is available at the SI data input is not acquired by the L1s. In cycle C5, the B clock pulses, causing L2 latches to acquire the data from the L1 latches. Note that the activation of the respective A/C and B clocks to operate the output SRLs in parallel mode occurs in separate cycles C4, C5. This is to ensure no clock overlap which would create a "flush" condition (i.e., passage of data without latching).
Then, during cycle C6, the SG signal input selects serial mode, such that the operational mode of the SRLs changes from parallel back to serial. In cycle C7 the data bits on the device under test primary output pins are acquired. Beginning in cycle C8, the data bits are scanned out from the output SRL chain 20 in the same manner as the test bits were scanned into the input SRL chain 10. That is, when the A/C clock pulses in cycle C8, the data bit from the L2 latch of the third SRL pair 22 is latched by the L1 of the fourth SRL pair 24 via the SI1 input. When the B clock pulses the data bit is latched by the L2 of the fourth SRL pair 24, for scanning out by the tester. At the same time, the L2 of the third SRL pair 22 has latched a data bit from a previous L1-L2 pair (if there is one).
In the standard stuck fault test cycle described above, a wide time window is presented that is not conducive to performance verification and transition fault testing. As shown in FIG. 2, the final bit test pattern starts propagating through the logic as soon as the B clock in cycle C2 activates. In order to provide a valid result, the data must reach the L1 latches of the output SRL's by the time the A/C clock deactivates in cycle C4. While this allocated propagation delay (hereinafter "test window",) indicated as "TP" in FIG. 2 may not appear to be troublesome, in practice each tester cycle can be up to 50.times. the width of the test machine cycle. As an example, if the clock pulses are 20 nanoseconds wide, the test window TP could be over one microsecond. Most of the time is allowed for settling. As a practical matter, depending on the chip processing technology, most logic circuits are designed to have a propagation delay of far less than the machine cycle. Thus, using conventional stuck fault LSSD clocking patterns, performance/transition fault testing cannot be accomplished.
The need for a performance test occurs at two different intervals in the manufacturing process. The first interval at which a performance test is needed is initial design verification. That is, when initial production parts are available, a performance test is needed to verify that both the logic design and the manufacturing process are capable of producing chips that meet the performance specifications. The second interval at which a performance test is needed is volume manufacturing screening. That is, during volume production, chips are analyzed to determine if (a) the particular chip meets the performance specification (i.e., no performance related defects), and (b) the manufacturing process is providing product on-spec.
Accordingly, there is a need in the art for a scan test that can provide both stuck fault and transition fault testing without adding appreciable complexity or expense to the overall test system.